This invention relates to the testing of integrated circuit chip devices by means of the weighted random pattern method. More particularly, the the present invention provides an on-product, self-test method for high quality testing which is efficient in terms of test coverage and also efficient in terms of the utilization of chip "real estate".
As integrated circuit chip devices have become more compact and have been produced with greater and greater levels of circuit density, the testing of these circuits for logic faults and other defects has become a difficult problem. Because of the complexity of the circuits produced on individual circuit chips, it has become very difficult, if not impossible, to provide a completely specified set of input test signals (generally referred to as test vectors) which fully covers all defects in the circuit. Storing such an extensive set of patterns is very restrictive in terms of the amount of memory that is required, even off-line, for such large amounts of data. Accordingly, designers have turned to pseudo-random pattern testing as one solution to the circuit test problem.
It should also be appreciated that in general, chip test methods are divisible into two classes: on-chip and off-chip. In the off-chip approach, test vectors are generated external to the chip (or product on a system or board level) and are supplied to the chip for test purposes. This approach has the advantage that the storage requirements for test data are less stringent than on-chip solutions. However, the off-chip approach suffers from the disadvantage that extra signal lines must be provided to access internal circuit input lines and circuit states.
Additionally, off-chip solutions also suffer from the disadvantage that such tests are performed on a onetime basis subsequent to chip manufacture and prior to product ship. There is no provision for further testing or diagnosis once the chip is in the field. This has two disadvantages. The first disadvantage is immediate and clear, namely that off-chip test methods are not able to provide diagnostic information with respect to chip failure in the field. Additionally, off-chip methods also are incapable of providing information concerning the nature of failures which do occur in the field. In terms of providing a closed loop method for identifying failures in the field with processes which are employed in the production environment, the off-chip testing solution provides little benefit.
Accordingly, it is seen that it is very desirable to be able to provide on-chip generation of test signals. Moreover, it is desirable that this goal be achieved with a minimum amount of test circuitry disposed on the chip itself. On the other hand, the circuitry is required to produce a large number of distinct test patterns which are effective but yet which are generated by means of circuitry which consumes little chip "real estate". This is desirable because it is more useful to employ the chip area for circuits which actually perform desired functions. Thus on-chip test circuitry should be simple, compact but yet effective.
Since it is possible to generate pseudo-random patterns using linear feedback shift register (LFSR) structures which are relatively compact in terms of circuit area requirements, such methods are employed in on-chip test situations. However, conventional random pattern self-test (RPST) methods do not always achieve consistently high fault coverage because of the presence of circuit faults which are resistant to random pattern testing. In these circumstances, flat random patterns eventually become highly ineffective. That is to say, a point is reached where thousands or even millions of patterns may be required to be generated in order to detect each additional fault. See for example, the article "Pseudo-Random Testing" in the IEEE Transactions on Computers, Vol. C-36, No. 3, March 1987 by K. D. Wagner, E. J. McCluskey and C. Chin. The fact that flat random pattern generators have fixed input "weights" of 1/2 does not contribute to their effectiveness. In particular, for such test methods, for any circuit input the probability of a logic 1 is equal to the probability of a logic 0 that is, 0.5.
Weighted random pattern test methods are costly to implement in terms of on-chip self-test methods. However, they can achieve high fault coverage. Weighted random pattern test methods and circuits are illustrated in the following documents: "Testability-Driven Random Test Pattern Generation" in the IEEE transactions on Computer-Aided Design, Vol. CAD-6, No. 6, 1987 by R. Lisanke, F. Brglez, A. Degeus and D. Gregory; "On Computing Optimized Input Probabilities for Random Tests" in the 24th IEEE Design Automation Conference, Paper 24.2, 1987 by H. J. Wunderlich; "Self-Test Using Unequiprobable Random Patterns" in the 17th IEEE Fault-Tolerant Computing Symposium, July, 1987 by H.-J. Wunderlich; "Self-Testing of Multichip Logic Modules" in the IEEE International Test Conference, Paper 9.3, 1982 by P. Bardell and W. McAnney; "Fault Simulation for Structured VLSI" in VLSI Systems Design, December, 1985 by J. Waicukauski, E. Eichelberger, et al.
Weighted random pattern test generators, such as those described in the documents cited above, produce one or more weight sets. A weight set specifies the weight to be used at each circuit input. With the input pattern probabilities suitably biased (towards producing more zeroes or more ones) according to the weights in the weight set, some random pattern resistant faults become more likely to be detected than by methods in which all inputs have weights set equal to 1/2. Several weighted random pattern algorithms exist to generate the desired weight sets. They differ in several aspects: (1) how to construct the next fault subset for weight generation, (2) how they resolve conflicting weighting requirements, (3) the minimum weight set effectiveness before it is discarded and a new weight set generated, and (4) the weight factor which expresses how many distinct weight resolutions are available. However, it becomes prohibitively expensive to implement weighted random pattern test generators and weight storage on-chip circuits as the weight factor, F, increases. The number of bits, B, required to specify each input weighting plus "fixed" weights of 0 and 1 is given by: EQU B=ceiling (log.sub.2 (2F+1)),
where the notation "ceiling" represents the greatest integer which is smaller than the quantity in parenthesis.